Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub- Expression Elimination for FIR Filter

This paper presents an efficient constant multiplier architecture based on vertical-horizontal binary common subexpression elimination (VHBCSE) algorithm for designing a reconfigurable finite impulse response (FIR) filter whose coefficients can rapidly change in real time. To design an efficient reconfigurable FIR filter, according to the proposed VHBCSE algorithm, 2-bit binary common sub-expression elimination(BCSE) algorithm has been applied vertically across adjacent coefficients on the 2-D space of the coefficient matrix initially, followed by applying variable-bit BCSE algorithm horizontally within each coefficient. Xilinx implementation results of multiplier show that the proposed VHBCSE algorithm is also successful in reducing the average power consumption by 9.9% along with an improvement in the area power product (APP) by 35% compared to 2-bit BCSE algorithm.